As semiconductor packaging technology develops toward miniaturization and high-density stacking, designs of semiconductor packages are starting to include implementation of redistribution layers for electrical connection of internal elements. Such semiconductor packages include wafer-level fan-out chip packages and panel-level fan-out chip packages. Fan-out chip packages can eliminate the thickness of the substrate. The fabrication process of the redistribution layer may be integrated in wafer-level packaging process or panel-level packaging process. As compared to conventional chip packaging process, the molding process is executed before the circuit is formed.
In conventional face-down fan-out chip packages, redistribution layers are fabricated on a surface of the encapsulation and on active surfaces of chips simultaneously. The circuitry of a redistribution layer may fan-out outside a chip area. However, the circuitry of the redistribution layer is vulnerable to cracking. Furthermore, when fan-out chip packages are implemented for 3D package stacking products such as Package-On-Package (POP) products, the requirements of the total package thickness is continuously increasing.